The CD4017 is a 5-stage divide-by-10 Johnson counter with 10 decoded outputs and a carry out bit.
The counter is cleared to zero count by a logical “1” on their reset line.
The counter is advanced on the positive edge of the clock signal when the clock enable signal is in the logical “0” state.
The configuration of the CD4017 permits medium speed operation and assures a hazard free counting sequence.
The 10 decoded outputs are normally in the logical “0” state and go to the logical “1” state only at their respective time slot.
Each decoded output remains high for 1 full clock cycle.
The carry-out signal completes a full cycle for every 10 clock input cycles and is used as a ripple carry signal to any succeeding stages.
- Package : SOP16
- Wide supply voltage range : 3V to 15V
- High noise immunity : 0.45 VDD (typ.)
- Low power Fan out of 2 driving 74L
- TTL compatibility : or 1 driving 74LS
- Medium speed operation: 5.0 MHz (typ.) with 10V VDD
- Low power: 10 µW (typ.)
- Fully static operation